View C32025_1223277.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

C32025 Digital Signal Processor Megafunction
Symbol
General Description
The C32025 is a 16-bit fixed-point digital signal processor core. It combines the flexibility of a high-speed controller with the numerical capability of an array processor. The C32025 has the same instruction set as the TMS320C25 and also provides the same interrupts, serial interface and timer. Developed for easy reuse with ASICs or FPGAs, the core requires under 18000 ASIC gates.
Applications
* * * * * *
Digital sound processing (adaptive filtering, FFT, other special sound effects) Voice recognition Telecommunications (modems, codecs) Medical equipment (diagnostics tools) Computers peripherals Various embedded data-intensive systems
CAST, Inc.
May 2004
Page 1
C32025 Megafunction Datasheet
Features
*
Control Unit o o 16-bit instruction decoding Repeat instructions for efficient use of program space and enhanced execution
o o
4K-words of internal ROM Internal 256-word RAM block configurable either as program or data space 64K-word external program space
o
*
Central Arithmetic-Logic Unit o o o o 16-bit parallel shifter; 32-bit arithmetic and logical operations 16 x 16 bit parallel multiplier with a 32-bit product 32-bit accumulator with output shifter Single-cycle Multiply-andAccumulate instructions
*
Data Memory organization o o o 2 Internal 256-word and one 32word RAM blocks 64K-words of external data space 6 memory mapped registers
* * *
16 Input and 16 Output channels Wait states for interfacing slower off-chip devices Multiprocessing support o o Global data memory interface Synchronization input for synchronous multiprocessor configurations
*
Auxiliary Registers o 8 16-bit registers for indirect addressing or temporary data storage 16-bit Auxiliary Register Arithmetic Unit including operations with reversed-carry propagation
o
* *
Concurrent DMA using an extended Hold operation Design is strictly synchronous with positiveedge clocking and synchronous reset, no internal tri-states.
*
Memory addressing modes o o o Direct - using a 9-bit Page Pointer and instruction word's lowest 7-bits Indirect - using the Auxiliary Register File Immediate - less than 16-bit via instruction word or full 16-bit long immediate following the instruction word Block moves for data/program management
o
* * * * *
8-level Hardware Stack Interrupt Controller: 6 interrupt sources, excluding reset and a software interrupt Synchronous serial port for direct codec interface 16-bit reload timer Program Memory organization
CAST, Inc.
Page 2
C32025 Megafunction Datasheet
Pin Description
Name
clk clkout1 clkout2 rs_n mpmc sync_n hold_n holda_n int0_n int1_n int2_n iack_n ps_o ds_o is_o ps_tri ds_tri is_tri rw_o rw_tri strb_o strb_tri ready bio_n br_n
Type
I O O I I I I O I I I I O O O O O O O O O O I I O
Polarity/
Bus size
Rise Low Fall Low Low Low/Fall Low/Fall Low/Fall Low Low Low Low High High High H Low High High Low Low
Description
Master clock input All internal synchronous circuits clock Master clock output (fclk/4) When High it indicates internal quarter-phases Q3 and Q4 Second clock output (fclk/4) When High it indicates internal quarter-phases Q2 and Q3 Hardware reset input Active for 2 cycles resets the device Microprocessor/microcomputer mode When Low the internal ROM is mapped into program space Synchronization input Forces the internal quarter-phase to Q1 Hold input Forces processor to place the data & address buses and control lines in the hi-Z state Hold acknowledge output Indicates that processor is in the hold mode External interrupt inputs External interrupt 0 External interrupt 1 External interrupt 2 Interrupt acknowledge Indicates branching to the interrupt vector Program, data and I/O space select signals Select signals tri-state control Enables external tri-state buffers Read/write output signal Indicates external transfer direction. High means reading Read/write tri-state control Enables external tri-state buffer Strobe signal Low indicates an external bus cycle Strobe tri-state control signal Enables external tri-state buffer Data ready input Indicates that external device is prepared for transfer to be completed Branch control input When active the BIOZ branch occurs Bus request output Asserted when the processor requires access to external global data memory space
CAST, Inc.
May 2004
Page 3
C32025 Megafunction Datasheet
Name
msc_n xf clkr clkx dr dx_o dx_tri fsr fsx_i fsx_o fsx_tri extaddr_o extaddr_tri extdata_i extdata_o extdata_tri romdata romaddr ram0data_i ram0data_o ram0addr ram0we ram0oe ram1data_i ram1data_o ram1addr ram1we ram1oe ram2data_i ram2data_o ram2addr ram2we ram2oe
Type
O O I I I O O I I O O O O I O O I O I O O O O I O O O O I O O O O
Polarity/
Bus size
Low Fall Rise High Fall Fall Fall High 16 High 16 16 High 16 12 16 16 8 High High 16 16 8 High High 16 16 5 High High
Description
Microstate complete output Indicates a completion of a memory operation External flag output General purpose output pin Receive clock input Transmit clock input Serial data receive input Data clocked by clkr Serial data transmit output Serial transmit tri-state control Active only while transmitting Frame synchronization pulse for receive input Frame synchronization pulse for transmit input Frame synchronization pulse for transmit output Frame synchronization pulse for transmit tri-state control External Program/ Data/ IO interface Address bus output Address tri-state control Data bus input Data bus output Data bus tri-state control Internal Program Memory interface Data input Address output Internal RAM 0 interface Data bus input Data bus output Data file address Data file write enable Data file output enable Internal RAM 1 interface Data bus input Data bus output Data file address Data file write enable Data file output enable Internal RAM 2 interface Data bus input Data bus output Data file address Data file write enable Data file output enable
CAST, Inc.
Page 4
C32025 Megafunction Datasheet
Block Diagram
u_phasegenerator clk rs_n sync_n clkout1 clkout2 extaddr_o extaddr_tri extdata_o extdata_i extdata_tri rw_o rw_tri strb_o strb_tri ds_o ds_tri ps_o ps_tri is_o is_tri ready ram0addr ram0data_o ram0data_i ram0oe ram0we ram1addr ram1data_o ram1data_i ram1oe ram1we ram2addr ram2data_o ram2data_i ram2oe ram2we romaddr romdata mpmc q1 Phase Generator Reset Control q3 q2 q4 rst u_auxreg ar0_reg ar1_reg ar2_reg ar3_reg ar4_reg ar5_reg ar6_reg ar7_reg st0_arp st1_arb external bus interface u_calu acch_reg accl_reg tr_reg block 0 interface pr_reg multiplier st1_sxm st1_c ALU Auxiliary Registers Unit arau
u_memdrivers Memory Control Unit st1_cnf
instructions
block 1 interface
st1_tc st1_pm st0_ov st0_ovm u_stack
shifters Central Arithmetic Logic Unit
progaddr
progbus
dataaddr
block 2 interface
databus (u_datam ux)
internal ROM interface u_irqdrivers timer tim_reg prd_reg drr_reg rsr_reg dxr_reg xsr_reg st0_intm imr_reg ifr_reg st1_fsm Interrupt Controller Peripherals
hardware stack Stack Unit u_control pc_reg pfc_reg qir_reg ir_reg rptc_reg mcs_reg dp_reg st1_hm st1_xf Control Unit FSM control unit xf_o hold_n holda_n bio_n msc_n
int0_n int1_n int2_n iack_n clkx dx_o dx_tri fsx_i fsx_o fsx_tri clkr dr fsr br_n
serial port receiver serial port transmitter external interrupts st1_fo st1_txm greg_reg
C32025 Block Diagram
CAST, Inc.
Page 5
C32025 Megafunction Datasheet
Functional Description
The C32025 core is partitioned into modules as described below.
Control Unit
Control unit consists of Program Counter (PC) and Prefetch Counter (PFC) used for program addressing and pipelining. Sequencer is responsible for data flow organization. Repeat Counter (RPTC) is used to repeat the execution of several instructions, especially data-intensive ones.
Memory Control Unit
It is an interface between the processor and all on-chip or off-chip memories. There are three internal RAM blocks interfaces, internal ROM interface and external address and data buses. External wait states are possible.
Central Arithmetic Logic Unit
Central Arithmetic-Logic Unit. (CALU) performs:
* * * *
Sign-extended shifting 32-bit arithmetic operations 32-bit logic operations 16-bit signed or unsigned multiplication
Auxiliary Registers Unit
Eight auxiliary registers are used for indirect data addressing or temporary data storage. Auxiliary Registers Arithmetic Unit performs operations on current auxiliary register after each indirect data memory read/write.
Stack Unit
Eight level hardware stack for PC storage during subroutine calls and interrupt service.
Peripherals
There is one 16-bit continuously operating timer with programmable period. Synchronous full-duplex serial interface can be used for interfacing serial AD/DA converters and codecs.
Interrupt Controller
There are three external interrupts, both edge and level triggered. Internal interrupt is generated at timer underflow or serial port transmit/receive completion. Those six interrupts are maskable using Interrupt Mask Register (IMR). There is also one non-maskable software interrupt.
CAST, Inc.
Page 6
C32025 Megafunction Datasheet
Phase Generator
Internal clock cycle divider. Machine cycle consists of four main clock cycles.
Reset Control
Reset input is sampled once a machine cycle and distributed all over the core.
Device Utilization & Performance
Supported Family
Flex Acex Apex Apex2 Cyclone Stratix Startix2
Notes: 1. 2.
Device Tested
EPF10K100E-1 EP1K100E-1 EP20K200E-1 EP2A15-7 EP1C6-6 EP1S10-5 EP2S15-3
LEs
4532 4532 4420 4528 4066 4370 3835
Utilization Memory
M4Ks; 1 M512 M4Ks; 1 M512 19 ESBs 19 ESBs 37 ESBs 7 EABs 7 EABs
DSP 1 1 -
Performance Fmax
24 MHz 26 MHZ 37 MHz 65 MHz 95 MHz 101 MHz 130 MHz
Implemented with 544x16 bit RAM and 4096 x 16 bit ROM Implemented with 544x16 bit RAM and 1048 x 16 bit ROM
Core Assumptions
The IACK_N and MSC_N lines are valid only during the quarter-phases Q1 and Q2 (when CLKOUT1 = 0). In other cases their behaviour is unpredictable in the original Texas Instruments TMS320C25 device. The C32025 sets them to 1s in Q3 and Q4, except in the hold mode when MSC_N remains 0. The original Texas Instruments TMS320C25 serial port doesn't re-start properly when a frame sync pulse occurs in the middle of a transmission. The new transfer following a re-start is interrupted in a moment when previous transmission should be completed as if and there were no frame sync pulses, but the transferred data is re-loaded. The C32025 serial interface works properly as it is described in the specification document. The CLKR and CLKX inputs are clock inputs in the original Texas Instruments TMS320C25 serial port registers. In C32025 they are not clock signals but are synchronously sampled at every positive edge of the main clock signal. The same applies to the external interrupts inputs INT0_N, INT1_N and INT2_N. They are connected to a negative edge flip-flop in the original device, but in C32025 they are sampled synchronously with
main clock signal. These changes cause delays in the serial port operation and forces the minimum length of an external interrupt pulse to at least one oscillator cycle. Some registers are not reset by RS_N in the original Texas Instruments TMS320C25 device, but are reset in the C32025. They are: ACC 00000000h PR 00000000h TR 0000h ARP 000 ARB 000 DP 000000000 IMR 000000 DRR DXR Stack OVM TC AR0-AR7 0000h 0000h all levels are reset to 0000h 0 0 all registers are reset to 0000h
CAST, Inc.
Page 7
C32025 Megafunction Datasheet
Verification Methods
The C32025 core's functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Texas Instruments TMS320C25 chip, and the results compared with the core's simulation outputs.
Development Environment
* * * * *
VHDL source code for the C32025 Synthesis support - Complete set of synthesis scripts for Synopsys Simulation support - A set of scripts and macros for Synopsys, MTI, and Aldec Example CHIP_C32025 - TMS320C25 compatible design This design uses the C32025 and illustrates how to build and connect memories and tri-state buffers Extensive HDL Test Bench that instantiates: o o o o o o Example design CHIP_C32025 External RAM External ROM External I/O Clock generator Process that compares your simulation results with the expected results
* * *
A collection of test assembler programs which are executed directly by the Test Bench A set of expected results Additional documentation o o o o Architectural overview Hardware description User Guide Design support including consulting
CAST, Inc.
Page 8
C32025 Megafunction Datasheet
Deliverables
Netlist Licenses HDL Source Licenses
* * * * * * * * *
Post-synthesis EDIF netlist Testbench (self-checking) Vectors for testbenches Expected results Place & Route script Simulation script Constraint file Instantiation templates User Documentation
* * * * * * *
Synthesizable VHDL or Verilog RTL source code Testbench (self-checking) Vectors for testbenches Expected results Simulation script Synthesis script User Documentation
Related Information
Texas Instruments URL: http://www.ti.com
Contact Information
CAST, Inc. 11 Stonewall Court Woodcliff Lake, New Jersey 07677 USA Phone: +1 201-391-8300 Fax: +1 201-391-8694 E-Mail: info@cast-inc.com URL: www.cast-inc.com
This megafunction developed by the processor experts at Evatronix SA
Copyright (c) CAST, Inc. 2004. All Rights Reserved. Contents subject to change without notice.
CAST, Inc.
Page 9

▲Up To Search▲

Price & Availability of C32025

	To Download C32025 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .